Regviz

NXP Semiconductors /LPC15xx /SYSCON /USBPLLCTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as USBPLLCTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC15xx/SYSCON/USBPLLCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MSEL0 (P_EQ_1)PSEL 0RESERVED

PSEL=P_EQ_1

Description

USB PLL control

Fields

MSEL

Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 111111: Division ratio M = 64.
PSEL

Post divider ratio P. The division ratio is 2 x P.

0 (P_EQ_1): P = 1

1 (P_EQ_2): P = 2

2 (P_EQ_4): P = 4

3 (P_EQ_8): P = 8
RESERVED

Reserved. Do not write ones to reserved bits.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data